In general, the present invention relates to devices and methods used in dry etching a surface of a wafer or substrate in semiconductor processing, and more particularly, to a novel dry etch confinement device that takes advantage of the so-called “hollow cathode effect” for operative arrangement within a substrate etching chamber apparatus that can be incorporated into an integrated cluster tool platform, if desired; and a novel method of dry etching a surface of a wafer substrate using such a confinement device with an etchant gas.
Microelectronics is that area of electronics technology associated with the fabrication of electronic systems or subsystems using extremely small (microcircuit) components. Since semiconductor fabrication and processing is driven by the computer-electronics industry, the demands for greater capability and faster data processing of smaller-sized computerized systems result in a demand for smaller-and-smaller integrated circuit (IC) microcircuits. Thus, precision IC processing is ever more important in microcircuit wafer fabrication.
The use of silicon and its oxide, along with photolithography, in semiconductor wafer fabrication dates back to the 1950's. The substrate for a microelectronic circuit is the base upon which the circuit is fabricated. A substrate must have sufficient mechanical strength to support its circuit(s) during fabrication, and substrate electrical characteristics depend on the type of microcircuit being fabricated. In general, hybrid microcircuits are deposited on substrates, and monolithic integrated circuits are formed within substrates. The substrates used in building hybrids are usually dielectric materials such as ceramics, glasses, or single-crystal insulators; and in some cases conductors or semiconductors coated with a dielectric layer are used. The substrates used for monolithic integrated circuits are semiconductor (e.g. silicon, GaAs) wafers (which can provide both electrical and mechanical-support functions) sliced from large single crystals, except in the case of special fabrication processes like silicon on sapphire.
Microcircuit wafer fabrication generally starts with a substrate to which layers, films, and coatings (such as photoresist) can be added or created (e.g., when fabricating a MOS monolithic IC, a silicon oxide layer is created on top of the silicon wafer), and from which these added or created materials can be subtractively etched (e.g., as in dry etching). Throughout semiconductor wafer fab, various processes are used to “clean” the wafers so that surfaces are reproducible and stable (see, generally, “Microelectronics: Processing and Device Design” by Prof. Roy A. Colclaser, John Wiley & Sons (1980), pg. 82).
More-particularly, in silicon wafer production, a well known process called chemical mechanical polishing (CMP) is widely being used to create a more planar outer top surface. Many integrated circuit fabrication modules introduce topographic non-planarity onto the wafers top surface. Examples include the formation of metal interconnect lines by metal deposition and patterning using photolithography and reactive ion etching. The subsequent dielectric deposition process preserves this non-planarity of the wafer top surface but this non-planarity is undesirable for subsequent photolithography patterning steps. To solve this problem, the deposited oxide thickness is increased compared to the desired final oxide thickness, and then this additional oxide is removed by CMP. In the case of oxide CMP, the wafer is polished using a colloidal suspension of fine SiO2 particles in an aqueous, alkaline “polishing” solution. The mechanical component of the polishing process causes material to be removed more rapidly from the high spots of the wafer surface which reduces the amplitude of any surface topography.
In the case of patterning (photo and etch) after dielectric deposition, the requirement for simultaneously clearing the circuit areas and the alignment marks makes dielectric etching difficult. For example, in dielectric via etching, it is difficult to develop an optimized etch process that simultaneously clears the vias and the alignment marks without over or underetching either. Even if an optimized dielectric etch process could be developed, certain thicknesses of dielectric over the alignment marks may create undesirable interference effects, making their recognition by the stepper alignment system difficult. This may necessitate the use of an extra photo-etch step to clear the dielectric over the alignment marks before attempting the patterning of the circuit. Thus it is advantageous to remove dielectric from over the alignment marks. The confinement device and associated method for selectively etching of the invention eliminates the need for an extra patterning step by using a two step etch that, first, clears out the alignment mark(s) in an etching chamber incorporating the novel confinement device and, then, performs a standard via etch in a subsequent conventional etch chamber.
Although CMP has a desired surface-planarization benefit (whether it is for dielectric or metal uniformity upon which successive layers can be built), an undesirable and costly side-effect of using CMP is that alignment marks required for subsequent photolithography steps are also “planarized”. When a subsequent metal layer is applied to the wafer above a planarized featureless surface, the alignment marks are no longer “visible” to the alignment sensors in the lithography tools, which require distinctive topography/contrast difference in the alignment mark scheme to operate. This is illustrated in FIGS. 2A-B, and associated background description in Column 2, of U.S. Pat. No. 5,705,320 issued to Hsu et al. which states that: “It is therefore essential that the IMD [inter-metal-dielectric layer 30] be cleared from the alignment mark areas and the metal layer from laser mark areas.” Good definition of alignment marks is necessary for proper pattern alignment in subsequent wafer fabrication steps.
Currently, to clear-out alignment marks/recesses filled-in after a planarization process, such as CMP, IC manufacturers often use a series of additional costly (complex and time-consuming) photolithography steps: Applying a marker clear-out photo resist (or photosensitive coating that adheres to the outer surface of the wafer), exposing the resist to ultraviolet light, developing the resist pattern, then etching the mark or recess using a plasma etching (e.g. reactive ion etching (RIE)) process, and finally adding a resist ash and cleaning step. Since the CMP process can be used several times throughout the fabrication of a single semiconductor wafer, and an alignment mark clear-out step is generally required after each CMP step to provide “redefinition” to every mark that has lost its distinctive recessed-topography, a single wafer can undergo several additional time-consuming photolithography clear-out steps. Therefore, in wafer fabrication, it is very desirable to find an alternative to having to perform (costly) photolithography alignment mark clear-out steps. The instant invention does just that.
U.S. Pat. No. 5,271,798 issued to Sandhu et al. In 1993, describes “the selective etching of tungsten by locally removing the tungsten from the alignment marks [normally a few-hundred microns in size] through wet etching without the need for any photo steps. Either before tungsten CMP or after, the wafers are flat aligned and tungsten etch solution is introduced through an enclosed etchant dispensing apparatus . . . [see column 2, lines 18-25].” After the wet etch, the etching byproduct is removed by suction and the wafer is cleaned by being rinsed in distilled water. “Wet etching” uses liquids (which have safety hazards and liquid waste disposal problems) and has limited uses in wafer fabrication.
FIG. 3 of U.S. Pat. No. 5,705,320 to the Hsu et al., mentioned above, shows a reticle 50 for a stepper which contains an image of the pattern for integrated circuit contact openings in the area 52. Located in the frame area 54, is a window 56 with dimensions of 3.5 mm×1.6 mm (column 4, lines 39-44). This patent continues, in column 4 through column 5:                The stepper senses the edges of the alignment 32 through the transparent insulative layer 30 and aligns the stage to position a first die in the focus of the reticle 50. After exposing the resist over the die to the contacts image, the stepper proceeds to expose the dice in a programmed sequence. When an alignment mark die 14 (FIG. 1) is reached, the stepper exposes the resist over the 3.5 mm×3.5 mm alignment mark region 16 by making three successive overlapping exposures through the clear-out window 56. During these exposures, four programmable mask blades located within the stepper restrict the exposing radiation to pass only through the clear-out window 56 preventing exposure from other portions of the reticle 50.Among other problems related with the Hsu et al. reticle 50 design and its associated process, neither are able to remove even a thin layer of tungsten within a recessed mark.        
Therefore, a new useful “dry” process and apparatus is needed that is capable of clearing-out, or re-defining, alignment marks/recesses on the order of for example, 30 μm to 5 mm across (in size) and 0.5 μm to 3.0 μm deep, which have effectively lost their distinctive topography during some part of the wafer fabrication process (such as during CMP). Without reasonable and cost-effective solutions at hand for recapturing the definition of wafer alignment marks which have partially (or wholly) lost their distinctive shape/topography, it is difficult (if not impossible) for wafer positioning mechanisms to precisely align wafers during wafer fabrication. Without accurate, reproducible wafer alignment during fabrication, precise specifications of the desired microcircuits cannot be met.
Plasmas are highly ionized gases which contain a mixture of electrically charged and neutral particles, and therefore, conduct electricity and react collectively to electromagnetic forces. By definition, the electron plus negative ion charge density and positive ion charge density are generally equal in a plasma. Plasmas are highly conductive and thus are nearly equi-potential regions, and they are always bounded by positive space charge regions known as plasma sheaths where the majority of any potential drops imposed across the plasma will occur. The sheath thickness “S” is given by the following solution to Poisson's equation, J. E. Allen in Plasma Physics, Institute of Physics Conference Series 20 (London Institute of Physics, London, 1974), at p. 136:                     S        =                                                                              ɛ                  0                                ⁢                k                ⁢                                                                   ⁢                                  T                  e                                                            2                ⁢                                  n                  s                                ⁢                                  q                  2                                                              ⁢                                    ∫              1                              (                                  q                  ⁢                                                                           ⁢                                      Δ                    /                    k                                    ⁢                                                                           ⁢                                      T                    e                                                  )                                      ⁢                                          ⅆ                x                                                                                  exp                    ⁡                                          (                                              -                        x                                            )                                                        -                  2                  +                                                            1                      +                                              2                        ⁢                        x                                                                                                                                                    Equation  [1]            where the edge of the sheath on the plasma side is defined as the point where the electron density falls by 1/ e relative to the plasma density at the point where quasineutrality breaks down (ns). This definition of the sheath edge was chosen because the sheath potential approaches the potential at the plasma edge asymptotically. In equation [1], q is the electronic charge, ε0 is the permittivity of free space, k is the Boltzmann constant, Te is the electron temperature, and Δ is the voltage drop across the sheath. This equation was derived for a DC sheath, but it approximately applies to an RF sheath if we understand S to be the time averaged thickness and Δ to be the time averaged voltage drop across the sheath. For a typical processing plasma, the plasma density in the center of the plasma is 1010 to 5×1011 cm−3 which corresponds to an edge of plasma density of ns=4×109 to 2×1011 cm−3. Typical electron temperature is 5 eV, and typical sheath voltage drops for RF biased sheaths over a range from about 50 to 500 V. Substituting these numbers into equation [1] yields typical sheath thickness of 0.025 to 1 cm, increasing as the voltage drop imposed across the sheath increases or the plasma density decreases.
In general, an electrode in contact with a plasma is referred to as a cathode whenever a large DC or RF voltage drop is imposed across the sheath adjacent to that electrode. If a cathode contains an aperture with a depth and diameter on the order of a few sheath thicknesses, then an intense plasma known as a hollow cathode discharge will form within and above the aperture because secondary and/or RF excited electrons are concentrated and confined in a small region. Additional background information on the so-called “hollow cathode effect”, can be found in Chapter 12 (pages 308-335 incorporated herein by reference) of the Handbook of Plasma Processing Technology, edited by Stephen M. Rossnagel, Jerome J. Cuomo, and William D. Westwood (Noyes Publications, NJ, 1990), see particularly section 12.2.2 (page 311 where “sheath” is mentioned) entitled “Hollow Cathode”. FIGS. 3 and 4 on pages 311 and 312 of this Handbook are schematics of a simple hollow cathode, “formed by confining a diode target with a similar opposing diode target.” FIG. 8 on page 314 of this Handbook is a schematic of a “super-confined hollow cathode”. Nowhere does the Handbook suggest suitability of the simplified cathode configurations for large-scale wafer production.
Currently-available dry etch plasma systems typically flow reactant gases into a vacuum chamber and apply an electric field at radio or microwave frequencies to electrodes to ionize the reactant gases and generate a plasma. Plasma reactants/radicals etch the substrate material intended to be removed. The electric energy applied to the supply gas entering a vacuum etching chamber may be from a capacitively coupled radio-frequency (RF) electrode, an inductively coupled RF source, a microwave generator (such as is used in electron cyclotron resonance (ECR) chambers), or other field generating source. Many types of plasma reactors currently exist: tunnel or barrel reactor; flat reactor (e.g., a pair of parallel electrode-plates); waveguide reactor (e.g., a downstream microwave generator); and so on. Relative to the mass of other particles within an etchant gas, electrons have a small mass and tend to absorb most of the energy gained from the electromagnetic field source. These high energy electrons collide with other particles, ionizing the etchant gas to sustain the plasma. Plasmas have been adapted for wide use in semiconductor wafer fabrication. For purposes of discussion, the wafer fab process referred to as “dry etching” has been classified into three subcategories of etching systems: (1) glow discharge methods (including “plasma etching” with low energy ion bombardment, Reactive Ion Etching, “RIE”, and glow discharge sputter etching which uses an inert gas plasma); (2) ion beam systems (including “ion milling”, chemical assisted ion milling, and reactive ion beam etching); and (3) down stream plasma etching where a plasma is used to generate radicals but where the substrate is not exposed to the plasma.
Capacitively coupled plasma discharges (characterized by relatively low ion densities) are widely used in integrated circuit manufacturing. RIE incorporates high RF power and high ion energy to attain fast etch rates. One current use of RIE is to etch vias into IC wafer layers. However, problems encountered in the current RIE systems include etch-induced substrate damage and low selectivity (usually attributed to the high energy ions). More-recently, semiconductor fabrication has been moving toward the use of high density plasma (HDP) sources. In general, HDP sources are combined with capacitively coupled wafer electrodes to provide independent control of the ion flux and ion energy. The main benefit of this configuration is high etch rates with a lower and controlled ion energy which can improve selectivity and reduce substrate/device damage.
Plasma surface treatment systems are now being used for cleaning or etching/surface modification in a variety of electronic environments: monolithic ICs (generally formed within silicon wafer substrates), hybrid microcircuits (usually deposited “on” wafer substrates), printed circuit boards (PCBs), ball grid arrays (BGAs) and surface mounted components, component lead frames, and flat panel displays.
Examples of different types of currently-available dry etch plasma systems include: the metal etch MxP CENTURA™ RIE vacuum plasma chamber distributed by Applied Materials, Inc. in Santa Clara, Calif.; Applied Materials, Inc.'s DPS inductively coupled plasma source; Applied Materials, Inc.'s AME 5000™ cluster tool; Technics Series 800 Micro™ RIE which uses RF signal to generate an RF plasma; the inductive transformer coupled plasma (TCP) planar helical coil reactor distributed by Lam Research Corporation in Milpitas, Calif.; a helical resonator plasma source (see D. L. Smith, Thin Film Deposition—Principles and Practice, McGraw-Hill, Inc. New York, (1995) p. 522); a helicon plasma source (see F. F. Chen, “Helicon Plasma Sources”, in High Density Plasma Sources, O. A. Popov, Editor, Noyes Publications, Park Ridge, N.J., (1995), p. 19.; or an ECR plasma source such as the MPDR 4325i™ ECR etch system distributed by Wavemat, Inc.
U.S. Pat. No. 5,693,234 issued to Peters in 1997 discloses a cup-shaped masking device 5 with a pedestal-shaped side part 5a and a cover part 5b with an aperture 6 through which there will be an incoming flow of etching gas radicals from reaction chamber 4. Reaction chamber 4 is located beyond hollow chamber 11 on the other side of aperture 6. A specific low pressure is set, which generally is so low that the mean free path length of the etching gas radicals produced in reaction chamber 4 is greater than the distance “a” from aperture 6 to substrate surface 9, and at least great enough that the etching gas radicals can traverse hollow cavity 11 to surface 9 (see Peters '234, column 4, lines 60-65). The gas radicals create, during the dry etching process disclosed by Peters, a recess 10 in substrate 9 with a depth contour t(r) that corresponds, to the deflection of a membrane (see Peters '234, column 3 through top of column 4). In the embodiments disclosed in Peters '234, etching of recess 10 requires the availability of etching gas radicals in reaction chamber 4 (located in the large space set off between electrodes 30 and 31 ). Halogen compounds are used as the etching gas (Peters continues in col. 4) because of the high reactivity of halogen radicals, especially fluorine and chlorine radicals. Masking device 5 is generally placed on substrate 8 as a whole before substrate 8 is introduced into receptacle 2. Typical dimensions for recess 10 (Peters '234 column 5) are 10 μm to 1 mm across (r0 r1 or R) and 5 μm maximum depth (t0).
U.S. Pat. No. 5,372,674 issued to Steinberg discloses an electrode 11 used in a plasma assisted chemical etching process having a cylindrical inner member 47 surrounded by a cylindrical outer member 45 defining an annular cylindrically-shaped gap 77 through which gas flows so that plasma discharge 43 comes into contact with top surface 48 of substrate 25 to etch a footprint 83 therein. A substantially horizontal chimney member 35, having a centrally located aperture 39, is mounted adjacent the bottom of electrode 71. Plasma discharge 43 forms between electrode 11 and substrate 25. Therefore, a top surface 48 of substrate 25 is in contact with plasma discharge 43 and is subject to a low energy ionic flux of less than 10 eV (see column 3, lines 22-42).
U.S. Pat. No. 5,627,105 issued to Delfino et al. discloses a process for making VIA interconnects on a partially processed semiconductor IC wafer (see, col. 6, line 56 through col 7, line 31). Delfino illustrates, in schematic form in FIG. 3, a cluster tool arrangement for passing wafers back and forth for processing. Delfino describes a “typical” wafer fab cluster tool as a multichamber vacuum system in which working chambers are arranged around a central transfer chamber. Each chamber of the cluster tool disclosed by Delfino is separated from the central transfer chamber by a gate valve with a vacuum lock. Several processing modules such as a rapid thermal processor (RTP) reactor 49, a pair of sputter modules 46, 47 used to deposit metallization for IC current paths, and an electron cyclotron resonance (ECR) microwave plasma apparatus (which can provide low pressure, high ion density at low ion energy), are illustrated.
U.S. Pat No. 5,667,592 (Boitnott et al.) discloses a four cluster modular wafer processing system having a wafer elevator chamber 12 for receiving a cassette 16 of wafers 18 (columns 2-3). A circular wafer handling chamber 28 has a multiple-spoke single-axis rigid-arm transfer carousel 30 that oscillates to transfer wafers 18 between a set of four processing station positions 31-34. Cylindrical metal sleeves 46-49 are lowered to allow the transfer of wafers 18 between adjacent processing stations 31-34 and raised and sealed to allow wafers 18 to be exposed to a particular removable process module top (39-42).
U.S. Pat. No. 5,567,255 issued to Steinberg discloses an inert outer chimney 13 disposed against a face of an annular electrode 11. Outer and inner chimneys 13, 14 confine the gas discharge from the annular electrode 11. The process gas 23 is introduced into annular electrode 11 at the center thereof without causing any secondary discharge, such as at inlet 19 where gas 23 enters bolt 15 from housing 12 (col. 3, lines 48-52). The etching footprint of the annular electrode 11 is a two inch outer diameter and a one inch inner diameter annulus.
In an effort to control the dry etching of a substrate layer of an IC wafer, the novel confinement device, associated system for dry etching, and method for selectively etching an identified localized area in a substrate, as contemplated and described herein, are designed for efficient selective etching through one or more layers to remove unwanted material (such as silicon, silicon-oxides, silicon nitride, and/or layered metals) without damaging or unnecessarily disturbing nearby wafer real estate and associated microcircuits and micro-components. The device, system, and method of the invention may replace costly photo etch steps currently used to clear-out alignment markers and other intended distinctive topographical features and can accommodate many different wafer sizes, many different substrate topographies, and many different etchant gases.
The new device, system, and method described herein, are suitable in operation with a wide range of standard wafer processing plasmas currently used in, and under development for, dry etching to remove unwanted materials from wafer substrate surfaces. This innovative device, system, and method are suitable for use within plasma chambers incorporated as part of an integrated cluster tool platform, or as a stand-alone unit. Furthermore, the simple, yet effective, design of this new device and system allow it to be tailored-to and installed with relative ease into currently-available plasma chambers.
Unlike the dry etch plasma systems currently available, the innovative device, system, and method of the invention utilize the so-called “hollow cathode effect”. None of the currently-available systems take full advantage of the relationship between plasma density, ion flux, and sheath thickness of a plasma, to selectively etch one or more substrate layers of a wafer while at the same time provide sufficient protection from disturbing nearby wafer real estate and any associated microcircuits and micro-components. In the spirit of this design, one, two, three apertures, and so on, can be added through the lower surface of the device of the invention and positioned as desired to selectively etch corresponding localized dielectric or metal areas in an underlying substrate layer(s), as will be further appreciated.